Referring to FIG. 1, which is a schematic view showing a thin film transistor array substrate in the prior art, the thin film transistor array substrate comprises common electrodes 102, gate lines 103, common electrode lines 104, and data lines 105. The common electrode lines 104 are connected to the common electrodes 102, so as to reduce the resistance of the common electrodes 102.
A method for manufacturing the thin film transistor array substrate with the above-mentioned structure comprises the following steps:
S11: forming the common electrodes on a substrate;
S12: forming a gate metal layer and the common electrode lines on the substrate with the common electrodes by a one-time patterning process, the gate metal layer including gate electrodes and gate lines;
S13: forming a gate insulating layer on the substrate with the gate metal layer and the common electrode lines;
S14: forming an active layer on the substrate with the gate insulating layer;
S15: forming a source/drain metal layer on the substrate with the active layer, the source/drain metal layer including source/drain electrodes and data lines;
S16: forming a passivation layer (PVX) on the substrate with the source/drain metal layer, and a via hole penetrating through the passivation layer and the gate insulating layer; and
S17: forming, on the substrate with the passivation layer, a pixel electrode layer, a first connection part for connecting pixel electrodes to the drain electrodes and a second connection part for connecting the adjacent common electrode lines on the gate metal layer.
Referring to FIG. 2, which is a schematic view showing a connection mode of the common electrode lines on the gate metal layer in the prior art. FIG. 2 includes: the substrate 101, the common electrode lines 104 arranged on an identical layer to the gate metal layer, the gate insulating layer 106, the passivation layer 107, the via holes 108 in the passivation layer, and the second connection part 109 arranged on an identical layer to the pixel electrode layer.
As shown in FIG. 2, the via hole 108 formed in the passivation layer 107 is relatively deep, so a rough surface will occur at the via hole 108, and an alignment layer (PI) will diffuse unevenly, thereby the image quality of a display panel will be affected seriously. For example, such undesirable phenomena as black Mura of the alignment layer at the periphery of the display panel, and M24 defects (with a plurality of vertical, linear Mura, blackening in the middle and whitening at both sides) and white spots (with discontinuous, dot-like black points) within a pixel region, will occur.
Hence, such problems as how to reduce the depth of the via holes in the array substrate and improve the uneven diffusion of the alignment layer urgently need to be addressed.